Sub-10nm high-K gate dielectrics for high-performance top-gated MoS2 transistors
Yu-Shu Lin1*, Kuei-Wen Huang1, Hsin-Chih Lin1, Miin-Jang Chen1
1Department of Materials Science and Engineering, National Taiwan University, Taipei, Taiwan
* Presenter:Yu-Shu Lin,
In two-dimensional transition metal dichalcogenides (TMDs) transistors, sub-10 nm high-K gate dielectrics play an important role. However, the lack of dangling bonds of TMDs gives rise to a lot of pinholes in gate dielectrics, which results in a large gate leakage current. In our work, sub-10nm, uniform, and pinhole-free Al2O3 high-K gate dielectrics on MoS2 is realized without any surface functionalization. An ultrathin Al2O3 layer, which was prepared by atomic layer deposition (ALD) with a short purge time at a low temperature of 80°C, offers nucleation cites for the onset of uniform deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals that the low-temperature nucleation layer leads to significant suppression of the gate leakage current. No oxidation of MoS2 was found in Raman and X-ray photoelectron spectroscopies, indicating that the deposition of the low-temperature Al2O3 nucleation layer would not cause damage on the MoS2 surface. Finally, low hysteresis and subthreshold swing are achieved in the normally-off top-gated MoS2 transistors with the high-quality sub-10nm Al2O3 high-K gate dielectrics.

Keywords: MoS2, two-dimensional materials, field-effect transistors, atomic layer deposition (ALD), high-K gate dielectrics